The presented VHDL implementation provides a bit deallocation in a round-robin fashion.
To create a priority arbiter, we just calculate the two’s complement of the request signal and bitwise AND the result with the request line (1). As result the least significant bit has the highest priority. This equation always returns the request with the highest priority.
(1) gnt <= req and not(req)+1;
To create a round robin arbiter we have to save the previous grant signal. This signal is used to masked out the previous grant signal (2) and use the method from (1) to get the least significant active bit.
(2) reqs <= req and not ((pre_gntM – 1) or pre_gntM);
(1) gnts <= reqs and not(reqs)+1;
The last step to realize the RR-Arbiter is to select between “gnt” and “gnts” (3). If all previous grant signals are masked we just start with the highest priority of equation (1). (3) gntM <= gnts when reqs /= 0 else gnt;
This technique can be used to create a round robin arbiter for any number of input bits by using the module below and some muxing-logic.